1. Field of the Invention
The present invention relates to a digital noise eliminator for eliminating pulsed noise signals beyond a predetermined frequency or below a predetermined period, and more specifically to a digital noise eliminator whose noise elimination time (noise pulse width or noise pulse frequency) can be determined by a shift time of a shift register activated in response to a reference clock. The noise eliminator is suitable for use for a multichannel communications system mounted on automotive vehicles, for instance.
2. Description of the Prior Art
An example of prior-art digital noise eliminators is disclosed in Japanese Published Unexamined (Kokai) Patent Application No. 61-7718, which is suitable for use to eliminate noise superimposed upon a synchronizing signal of a TV set, as shown in FIG. 1(A).
This prior-art noise eliminator includes a flip-flop 2, an AND gate 4, a counter flip-flop 6, a one-shot multivibrator composed of two NOR gates 8 and 12, an inverter 14, and another AND gate 10, and operates according to the timing chart shown in FIG. 1(B). In more detail, the above one-shot multivibrator generates a one shot pulse OUT with a pulse width t in response to an up-edge of an input signal Q.sub.n. In order to prevent the multivibrator gates 8 and 12 from being activated in response to noise, the counter flip-flop 6 counts output signals of the AND gate 4 only when the input signal IN is at "1" and the output signal OUT is at "0", and a one-shot pulse is generated at a time when the counter 6 counts a predetermined number of the AND gate output signals. In this prior-art circuit however, although noise A generated when the output signal is at "0" as shown in FIG. 1(C) can be eliminated, it is impossible to eliminate noise B generated when the output signal is at "1" as shown in FIG. 1(C).
Therefore, under the environment where various noises are always generated due to interference between one signal harness and the other signal harness, for instance, such as within an automotive vehicle, there still exists a problem in that it is difficult to eliminate noise sufficiently.
Another example of prior-art digital noise eliminator is disclosed in Japanese Published Unexamined (Kokai) Utility Model Application No. 61-75637, as shown in FIGS. 2(A) and (B), which can eliminate input signals having frequencies more than a predetermined value.
In FIG. 2(A), this noise eliminator 1 includes a P-channel MOS FET 3, an N-channel MOS FET 5, an inverter 17, a NAND gate 19, a NOR gate 21, another P-channel MOS FET 23, another N-channel MOS FET 25, a capacitor 11 and another inverter 13. Further, in FIG. 2(A) the reference numeral 7 denotes an input terminal, 15 denotes an output terminal, and 9 denotes a supply voltage terminal.
The operation of the circuit shown in FIG. 2(A) will be described hereinbelow with reference to FIG. 2(B). When an input signal changes from a low-voltage level ("L") to a high-voltage level ("H"), since the N-MOS FET 5 is turned on, the capacitor 11 is discharged via the N-MOS FET 5, so that the voltage level at node 26 gradually drops as shown. In this case, when the H-level of the input signal is wide enough and therefore the voltage level at node 26 drops down to a threshold 30 of the NOR gate 21, since the N-MOS FET 25 is further turned on, the capacitor 11 is discharged immediately down to "L", so that the output terminal changes to "H" normally via the inverter 13. However, when the input signal changes from "H" to "L" abnormally due to noise before the voltage level at node 26 reaches the threshold 30 of the NOR gate 21, since the P-MOS FET 3 is turned on, the capacitor 11 is charged immediately, so that the output terminal 15 changes to "L" via the inverter 13.
In contrast, when the input signal changes from "H" to "L", since the P-MOS FET 3 is turned on, the capacitor 11 is changed via the P-MOS FET 3, so that the voltage level at node 26 rises as shown. In this case, the L-level of the input signal is wide enough and therefore the voltage level at node 26 rises up to a threshold 31 of the NAND gate 19, since the P-MOS FET 23 is simultaneously turned on, the capacitor 11 is changes immediately up to "H", so that the output terminal changes to "L" normally via the inverter 13. However, when the input signal changes from "L" to "H" abnormally due to noise before the voltage level at node 26 reaches the threshold 31 of the NAND gate 19, since the N-MOS FET 25 is turned on, the capacitor 11 is discharged immediately, so that the output terminal 15 changes to "H" via the inverter 13.
In the above-mentioned prior-art circuit, therefore, it is possible to eliminate a noise pulse having a pulse width shorter than that determined on the basis of a time constant of the discharging circuit composed of the capacitor 11 and the N-MOS FET 5 or the charging circuit composed of the capacitor 11 and the P-MOS FET 3, irrespective of "H" or "L" level signals.
In the above-mentioned second prior-art noise eliminator, however, since the noise eliminating time period (or the eliminatable noise pulse width or frequency) is determined by the time constants (variation) in the manufacturing process and further temperature and voltage fluctuations. Therefore, there exists a problem in that the noise eliminating effect is not sufficient when the difference in frequency or period between the normal pulse and noise is small. In addition, when a long noise eliminating time period is required, since the long time-constant transistors and the large capacitors increase in volume, there exists another problem in that the IC chip volume increases and therefore the cost thereof is high when the prior-art circuit is integrated into a single IC chip.